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AnalogX Announces World’s Lowest Power SERDES IP in 7nm and 6nm and Expansion Plan

AnalogX, the leading provider of multi-standard connectivity SerDes IP solutions, today announces the availability of its silicon-proven 7nm & 6nm SERDES. AnalogX is the market leader in low-power SERDES IP, serving the chiplet and chip-interconnect market with 16nm, 12nm, and now 7 nm & 6 nm technology nodes. The company also

HDL Design House Partners with Marketing Platform AnySilicon

AnySilicon, the leading marketplace for ASIC service providers, announced today that HDL Design House, a leading-edge digital, analog, and back-end design and verification services provider, has joined AnySilicon to promote its design services. As part of the AnySilicon platform, HDL Design House will gain access to a full range of

Webinar – High End Electronics meets Optics

AEMtec GmbH located in Berlin Germany provides a new 2021 Eight Session Webinar Series “Next Level of Technology – High End Electronics meets Optics”. Launch of webinar series in February. New industry trends, technology portfolio, implementation strategies as well as already successfully generated applications will be shown. The participant receives the

Protocol and Interface Agnostic Universal D2D Controller for HPC and Chiplets

Demand for die-to-die and chip-to-chip interfaces has been growing steadily in the past few years due to new applications in cloud/data centers, AI (training and edge applications), and High-Performance Computing (HPC). The demand is driven by the requirements of high throughput, low latency and low power in these applications. Advances in packaging technology are further helping the

VeriSilicon Partner with AnySilicon

AnySilicon, the leading marketplace for ASIC service providers, announced today that VeriSilicon, an all-round, one-stop custom silicon services and semiconductor IP licensing services provider, has joined AnySilicon to promote its ASIC development services and IP cores. As part of the AnySilicon platform, VeriSilicon will gain access to a full range

The Ultimate Guide to Static Timing Analysis (STA)

Static Timing Analysis is defined as: a timing verification that ensures whether the various circuit timing are meeting the various timing requirements.

One of the most important and challenging aspect in the ASIC/FPGA design flow is timing closure. Timing closure can be viewed as timing verification of the digital

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AnalogX Announces World’s Lowest Power SERDES IP in 7nm and 6nm and Expansion Plan

HDL Design House Partners with Marketing Platform AnySilicon

Webinar – High End Electronics meets Optics

Protocol and Interface Agnostic Universal D2D Controller for HPC and Chiplets

VeriSilicon Partner with AnySilicon

The Ultimate Guide to Static Timing Analysis (STA)

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Blog

AnalogX Announces World’s Lowest Power SERDES IP in 7nm and 6nm and Expansion Plan

HDL Design House Partners with Marketing Platform AnySilicon

Webinar – High End Electronics meets Optics

Protocol and Interface Agnostic Universal D2D Controller for HPC and Chiplets

VeriSilicon Partner with AnySilicon

The Ultimate Guide to Static Timing Analysis (STA)

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