Category Archives: ASIC Design

Maximizing SoC Longevity with PCIe 3.0: A Designer’s Guide

Direction Uncertainty

As PCIe 5.0 and 6.0 dominate headlines in the semiconductor industry, it’s tempting for every SoC design team to reach for the newest protocol available. But not every application needs blazing-fast 32GT/s throughput—and not every market segment can afford the power, complexity, and cost penalties that come with bleeding-edge PHYs.
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Three Ethernet Design Challenges in Industrial Automation

Conveyor for the production of television sets.

As factories, process plants, and robotics platforms become increasingly intelligent and interconnected, the demand for stable, low-latency data links has pushed Ethernet deeper into embedded systems. However, since designing Ethernet connectivity into industrial chips comes with its technical and logistical hurdles, engineers may face challenges when implementing Ethernet in industrial

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Key ASIC Berhad Signs RM1.11 Million Contract to Jointly Develop AI-Driven, Ultra-Low Power RF Navigation Chip with Middle East Partner

press release chip

Kuala Lumpur, Malaysia – September 30, 2025 – Key ASIC Berhad (“Key ASIC” or “the Company”), a leader in ASIC design and innovation, has signed a contract worth RM1.11 million with a navigation systems company in the Middle East to jointly develop an AI-driven RF-integrated navigation chip.
 
 
The

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The 3 Hidden Risks That Can Derail Your IC Design Project! How to Avoid Them?

CPU chip installed on a computer motherboard

As more companies pursue ASICs to gain product-level differentiation, the ASIC road from concept to chip is paved with unseen challenges.
Many design teams, especially startups or system OEMs new to silicon, encounter the same pitfalls that delay projects, drain budgets, or derail product timelines.
 
Based on our experience

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Synopsys Collaborates with TSMC to Drive the Next Wave of AI and Multi-Die Innovation

press release wafer

Sept. 25, 2025 – 
SUNNYVALE, Calif. —   — Synopsys, Inc. (Nasdaq: SNPS) announced today its ongoing close collaboration with TSMC to deliver multi-die solutions, encompassing advanced EDA and IP products, that support TSMC’s leading-edge processes and packaging technologies, driving innovation in AI chip and multi-die design. The 3DIC Compiler exploration-to-signoff platform and IP, tuned for

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EnSilica and Codasip announce strategic partnership

news

Sept. 23, 2025 – 
EnSilica and Codasip announce strategic partnership to bring CHERI cybersecurity to automotive, critical national infrastructure, defence and aerospace applications
 
Oxfordshire, United Kingdom and Munich, Germany –  EnSilica, a fabless supplier of mixed-signal and digital ASICs, and Codasip, a provider of functionally-safe and cyber-resilient RISC-V CPUs, announces

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