I think this is an appropriate first post, because this is a question that we’ve heard many times when talking with hardware engineers trying to sell our product. The fact that there are (now) about a dozen companies trying to replace RTL with alternatives (I’ll talk about HLS in other
Read More
Die Per Wafer (DPW) online calculator is free and available live on AnySilicon website. The die per wafer calculator is simple to use and very accurate, however the results are estimates.
Now when you have the number of dies per wafer, you may want to consider:
See
Last week’s post was addressed primarily to those of you who are already designing SoCs. We made the point that more and more SoCs have multiple processors, either homogenous or heterogeneous, and that most or all of those processors do or will have caches. This led to the main conclusions of the
Read More
This is a guest post by Dolphin Integration which provides IP core, EDA tool and ASIC/SoC design service.
This is a guest post by Methodics that delivers state-of-the-art semiconductor data management (DM) for analog, digital and SoC design teams.
The topic of IP quality in the SoC era is difficult to define, and solutions to problems relating to IP quality, verification, and use are hard to find. Debates rage between IP users, suppliers,
Read More
This paper describes the use of behavioral models and mixed-signal simulation as a means to verify the proper instantiation, connectivity and control of analog and mixed-signal (AMS) intellectual property (IP), and also as a means to prototype an AMS integrated circuit (IC) or system-on-chip (SOC) using behavioral models in place
Read More