This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India.
Electrostatic Discharge and Electromigration might sound similar, but refer to two different physical phenomena. Let’s take them up one by one.
Electrostatic Discharge (ESD) is the large current flow between any
This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India.
Lock-Up Latches are important elements for STA engineer while closing timing on their DFT Modes: particularly the hold timing closure of the Shift Mode. While shifting, the scan chains
Semiconductor foundries claim they release a new technology node every two years. They may be off by a year or two, but on the whole, this is quite impressive, no doubt. Come to think of it, I don’t believe many of us even change our mobile phone every two years. How
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With the increased complexity of SoC designs, high tapeout prices and shrinking time-to-market, ASIC Prototyping has become a key step in ASIC projects. FPGA development boards are being used more often to verify ASIC design, test hardware and software integration, and provide a proof of concept demonstration to potential customers
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The following infographics shows Synopsys’s mergers and acquisitions along the years from its very beginning. Synopsys was founded in 1986 by David Gregory, Aart de Geus and has been involved with many mergers and acquisitions.
The very recent large acquisitions include:
2008
Synplicity
ChipIT
2009
ChipIdea
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Calculating the number of Dies Per Wafer (DPW) is a very simple and straight forward task. It’s actually based on basic high school mathematics which are related to circle area formula, remember Pi?
Silicon dies which are placed on a wafer can also be described as many