Category Archives: ASIC Design

Die Per Wafer (free) Calculator – trusted by GF and Amkor

chip-size-calculator

 
Calculating the number of Dies Per Wafer (DPW) is a very simple and straight forward task. It’s actually based on basic high school mathematics which are related to circle area formula, remember Pi?
 
Silicon dies which are placed on a wafer can also be described as many

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Cadence Mergers and Acquisitions History [infographic]

The following infographics shows Cadence’s mergers and acquisitions along the years from its very beginning.
Cadence Design Systems was founded in 1988 by the merger of SDA Systems and ECAD and has been involved with 100 mergers and acquisitions. The very recent and large acquisitions are:
Year 2013

Tensilica
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A Simple Method for Choosing ASIC Design Services

Two funny scientists

In 2005 I applied for a job in Singapore. The job required some technical and business skills and therefore the interview was a bit tricky.
One part of the interview related to estimating market size. They asked me to estimate the number of Piano Tuning companies which are currently active

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Six ways to improve chip yield rate- before the project starts

pink piggy bank sits atop a black calculator

Early on in Chip projects, yield is not taken very seriously. The common thinking goes –  anyhow there isn’t much to do as this early point of time. However, there are actually several things you can do even before the Chip design starts, which will translate to clear savings.

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