Category Archives: Blog

Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its digital, signoff and custom/analog tools have achieved V1.0 Design Rule Manual (DRM) and SPICE certification from TSMC for its 10-nanometer (nm) FinFET process. Cadence and TSMC are also continuing to collaborate on the advancement of 7nm technologies and have completed

ASIC Design Flow – an Overview

Today, ASIC design flow is a very solid and mature process. The overall ASIC design flow and the various steps within the ASIC design flow have proven to be both practical and robust in multi-millions ASIC designs until now.
Each and every step of the ASIC design flow has a

Choosing IP core – It’s not just the product, it’s the relationship

This is a guest post by PLDA which designs and sells intellectual property (IP) cores and prototyping tools for ASIC and FPGA

You are on a very strict schedule for your next chip. Not wanting to reinvent the wheel, you plan to go to an outside vendor for some of your