Category Archives: IP Cores

Actions Technology’s smart watch SoC adopted VeriSilicon’s 2.5D GPU IP

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Shanghai, China, May 15, 2024–VeriSilicon (688521.SH) today announced that Actions Technology (688049.SH), a low-power AIoT fabless semiconductor company, has adopted VeriSilicon’s power-efficient and feature-rich 2.5D Graphics Processor Unit (GPU) IP in its highly integrated dual-mode Bluetooth smart watch SoC series, ATS3085S and ATS3089.
 
Featuring low power consumption and high frame rate,

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Silvaco Announces Launch of Initial Public Offering

Santa Clara, CA – April 30, 2024 — Silvaco Group, Inc. (“Silvaco”), a provider of TCAD, EDA software, and SIP solutions that enable semiconductor design and AI through software and innovation, today announced it has launched the roadshow for its initial public offering (“IPO”) of 6,000,000 shares of its common stock.

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VeriSilicon’s complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification

press release

Shanghai, China, March 28, 2024 — VeriSilicon (688521.SH) today announced its complete Bluetooth Low Energy (BLE) IP solution has achieved full compliance with LE Audio specification, including certifications for the LE Audio protocol stack and Low Complexity Communications Codec (LC3). This solution is applicable to mobile phones, Bluetooth earphones including True

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QuickLogic Signs 7-Figure eFPGA IP Contract for GlobalFoundries’ 12LP Process

press release

AN JOSE, Calif., Feb. 28, 2024 — QuickLogic Corporation (NASDAQ: QUIK), a leading developer of embedded FPGA (eFPGA) IP and User Tools, ruggedized FPGAs, and Endpoint AI/ML solutions, is proud to announce its selection by a top-tier Defense Industrial Base company for eFPGA IP targeting the GlobalFoundries’ 12LP, 12nm low-power process.

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Noesis Technologies releases its Ultra High Speed FFT/IFFT processor IP Core

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February 26, 2024 — Noesis Technologies has announced today the immediate availability of its ntFFT_UHS IP Core that implements a customized FFT/IFFT programmable fixed point (Decimation in Frequency – DIF) transform processor, supporting low latency, streaming, ultra-parallel complex samples per clock cycle in natural order. Input, internal and output 2’s complement

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RISC-V Processors Addressing Edge AI Devices to Reach 129 Million Shipments by 2030

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LONDON, Feb. 14, 2024 — Reduced Instruction Set Computing (RISC)-V processor architectures are starting to address edge Artificial Intelligence (AI) workloads, and this trend is set to continue throughout the decade. According to a new report from global technology intelligence firm ABI Research, while RISC-V’s penetration into AI workloads is only just beginning,

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