Category Archives: Packaging

Copper Wire (Cu) Bonding Reduces Package Cost

copper-wire-bonding

Do you know someone that is not eager to reduce their ASIC production costs? I don’t.  Some say that redesign changes can lead to significant cost reduction, for instance – using a more advanced silicon technology node to shrink the die size. True, but this is a really big, painful

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BGA Substrate Design

Very often IC package design requires designing a BGA substrate. Substrate design and layout is very similar to any other PCB design. The difference is that the substrate size is much smaller than most of the PCBs you have seen. In this post we do something a bit unusual and

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Moisture Sensitivity Level and Popcorn Effect

MSL stands for Moisture Sensitivity Level. It represent the amount of time an IC can be exposed to ambient conditions and still be assembled on a PCB without being damaged.

When the antistatic bag is opened and the ICs are exposed to ambient conditions, the moisture in the air

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What Are The Top 3 Recommended Chip Package Types Today?

If you are debating which package type would fit best to your ASIC project, perhaps this article can help you narrow down the various options. In the semiconductor industry today there are three types of packages recommended for new designs:
QFN
Quad Flat No Leads. These are SMT packages, which

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