Category Archives: Qualification

Understanding High Temperature Storage Life (HTSL) in IC Qualification

April 15, 2018, anysilicon

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For ASIC or IC, there are recommended environmental conditions for their storage which allows them to perform at proper functionally. However, it is well known that storage may not always be close to the recommended standard. This is where the high temperature storage life (HTSL) test comes into play, testing

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Understanding Highly Accelerated Stress Test (HAST) in IC Qualification

April 15, 2018, anysilicon

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The highly accelerated stress test (HAST) involves the effects of humidity and temperature on an IC or ASIC. The HAST is designed to test the package of the ASIC under extreme humidity and temperature conditions. Devices that pass such tests will be able to withstand the normal rigors of temperature

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Understanding ESD CDM in IC Design

April 15, 2018, anysilicon

esd

In addition to the human body model (HBM) which is used to measure the electro-static discharge (ESD) that may affect IC/ASIC devices, there is also damage that may come from charged device model (CDM) which also must be tested. Although superficially similar to the HBM, the CDM is different and

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Understanding ESD HBM in IC Design

April 15, 2018, anysilicon

esd

In building integrated circuits (ICs) or ASICs, one area of concern is how they are protected from outside electrical sources. While most systems are geared towards power overloads, one source that may cause considerable damage is the electro-static discharge (ESD) that comes from the human body. To help test for

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Managing IC Qualification – A Quick Guide

March 31, 2018, anysilicon

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Many IC designers pay little attention to IC qualification and consequently pay high price and delays before the chip reaches to high volume. The mindset of experienced IC designers is considering IC quality (and production test) through all phases of the IC design process. Today, more than ever, re-tapeout is

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How to bulletproof your ASIC Design

February 11, 2016, anysilicon

crystal ball

As the ASIC design is moving towards maskset creation and tapeout, the cost of design changes are increasing exponentially.  It’s easier and cheaper to modify the ASIC design and even redo some of the chip architecture early the design stage. However it’s much more difficult and far more expensive after

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