Choosing between 28nm, 40nm, and 65nm is one of the most common — and most underestimated — decisions in ASIC development.
These nodes dominate industrial, automotive, consumer, and IoT ASICs, yet teams often choose based on habit or outdated assumptions. In reality, the differences between 28nm, 40nm, and 65nm
Choosing a 22nm process node is not just a scaling decision — it is a strategic choice that affects power consumption, cost structure, ecosystem access, and long-term product risk.
For many ASIC and SoC teams, 22nm sits at the crossroads between mature nodes (28nm/40nm) and more advanced, higher-risk technologies.
28nm is a turning point in ASIC development. It is often described as a “mature advanced node,” but in practice it represents the last node where many non-hyperscale teams can realistically operate. Beyond 28nm, ASIC economics, risk, and organizational requirements change dramatically.
This article explains what drives 28nm wafer and
40nm is often the first node where advanced-node realities become unavoidable. While still planar, 40nm introduces a level of complexity, cost sensitivity, and schedule risk that is very different from 55nm and above. As a result, cost assumptions at 40nm are frequently optimistic — especially for first-time ASIC teams.
This
55nm sits firmly in the advanced planar node category. While it is often grouped with 65nm, in practice it behaves very differently — especially in terms of cost sensitivity, schedule risk, and MPW limitations.
This article explains what drives 55nm wafer and MPW cost, and when MPW is still
90nm is often misunderstood. It is sometimes treated like a “slightly smaller 130nm,” but in practice it behaves much closer to a transition node — especially in terms of cost sensitivity, design discipline, and backend impact.
This article explains how 90nm wafer and MPW costs really work, and when