Category Archives: Wafer and Foundries
Major Pure-Play Foundries Revenue Per Wafer 2017-2018
The average revenue generated from processed wafers among the four biggest pure-play foundries (TSMC, GlobalFoundries, UMC, and SMIC) is expected to be $1,138 in 2018, when expressed in 200mm-equivalent wafers, which is essentially flat from $1,136 in 2017, according to a new analysis by IC Insights (Figure 1). The average
Read MorePure-Play Semiconductor Foundry Market Growth By Region 2017-2018
IC Insights’ September Update to The McClean Report shows that as a result of a 51% forecasted increase in the China pure-play foundry market this year (Figure 1), China’s total share of the 2018 pure-play foundry market is expected to jump by five percentage points to 19%, exceeding the share held by the rest
Read MoreWorldwide Location of Wafer Fabs – Interactive Map
Wafer fabs are the backbone of every electronic product. Every chip consists of a piece of silicon that is produced in a wafer fab. Wafer fabs play a key role in the customer, medical and automotive markets because the are they enabler of innovative technologies.
There are many wafer
GLOBALFOUNDRIES Reshapes Technology Portfolio to Intensify Focus on Growing Demand for Differentiated Offerings
GLOBALFOUNDRIES today announced an important step in its transformation, continuing the trajectory launched with the appointment of Tom Caulfield as CEO earlier this year. In line with the strategic direction Caulfield has articulated, GF is reshaping its technology portfolio to intensify its focus on delivering truly differentiated offerings for clients
Read MoreFaraday ASIC Service Leverages Samsung FinFET Platform to Target Next-generation Applications
Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today announced that it is leveraging Samsung FinFET platforms to extend its ASIC design solutions in next-generation applications, such as artificial intelligence (AI), 5G/infrastructure networking, blockchain, cloud storage, high-performance computing (HPC), AR & VR, and high-end imaging.
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IBM and Synopsys Accelerate 3nm Process Development with DTCO Innovations
Synopsys, Inc. (Nasdaq: SNPS) today announced a collaboration with IBM to apply design technology co-optimization (DTCO) to the pathfinding of new semiconductor process technologies for the 3-nanometer (nm) process node and beyond. DTCO is a methodology for efficiently evaluating and down-selecting new transistor architectures, materials and other process technology innovations
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