Maskset cost is becoming one of the major expenses to the overall NRE cost of ASIC projects, particularly with advanced technology nodes. For projects targeting low volume production the maskset cost is a financial barrier to a profitable and solid business.
Taping out using MLM instead of a full maskset
Semiconductor foundries claim they release a new technology node every two years. They may be off by a year or two, but on the whole, this is quite impressive, no doubt. Come to think of it, I don’t believe many of us even change our mobile phone every two years. How
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Two years ago TSMC announced its plans to expand into IC packaging services. It is unclear how much these plans succeeded up till now, but it definitely seems that TSMC is now in an excellent position to take a big bite into the advanced IC packaging market, enter into direct competition
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What is a die per wafer calculator?
A die per wafer calculator is a tool used by chip designers and fabs to estimate how many individual dies (aka chips) can be cut from a single semiconductor wafer.
It’s like trying to fit as many square stickers as possible on
Process Lots (or corner lots) are special-modified-wafers that help verifying chip design robustness to accommodate process variations that statistically occur in wafer production over the years.
One of the products that semiconductor foundries offer is process lots (also called: corner lots, split lots or skewed lots). Corner lots wafers are
I have the utmost respect for TSMC. For their advanced technology; for the quality of their products; for their ecosystem; and for their contribution to the industry. In fact, TSMC has become so big – that it will take a while until the second ranked foundry can catch up.
The