ASIC Design Engineer – Pixel IP

Join Apple's Hardware Technologies group as an ASIC Design Engineer in the Pixel IP design team, where you'll create high-performance, power-efficient system-on-chips (SoCs) that enhance the user experience of Apple products. This role focuses on designing digital signal processing pipelines for capturing and displaying images and video, ensuring seamless functionality for millions of customers.

Responsibilities:

• Design high-quality RTL for digital hardware with embedded assertions and cover points.
• Write detailed micro-architectural specifications.
• Collaborate with cross-functional teams to optimize performance while minimizing power and area.
• Synthesize designs and optimize for power, timing, and area.
• Work with design verification and formal verification teams to debug and verify functionality and performance.

Qualifications:

• Bachelor's Degree in Electrical Engineering or Computer Engineering.
• Knowledge of front-end ASIC RTL digital logic design using Verilog or System Verilog.

Skills:

• Strong problem-solving skills in computer architecture fundamentals such as finite state machines and pipelining.
• Excellent collaboration and communication skills, both written and verbal.
• Familiarity with on-chip bus protocols like AMBA (AXI, AHB, APB).
• Knowledge of synthesis and timing/area/power analysis tasks.
• Familiarity with scripting languages (Python, Perl, TCL).
• Experience with High-Level Synthesis and hardware design using SystemC/C++ is a plus.
• Background in digital signal processing concepts is a plus.