ASIC Design Engineer, Senior

Join TEL as a key contributor in the design and implementation of custom VLSI test chips. This role involves developing automation scripts, performing verification simulations, and collaborating with engineering teams to ensure seamless integration of ASIC designs.

Responsibilities:

• Support the design and implementation of custom VLSI test chips.
• Develop Python-based scripts to automate schematic and layout tasks for custom ASIC circuits.
• Complete top-level chip layout and physical verification.
• Perform pre-silicon verification simulations, including RTL verification.
• Collaborate closely with EDA tool providers and test engineering teams.
• Assist in the design and verification of both RTL and analog circuit blocks to ensure seamless integration within ASIC designs.

Qualifications:

• Bachelor’s degree (or equivalent) in Electrical Engineering, Computer Engineering, or Computer Science required.
• B.S. with 5+ years or M.S. with 2+ years of relevant industry experience preferred.
• Experience with scientific Python libraries such as numpy, pandas, and matplotlib is desired.
• Hands-on experience or familiarity with RTL design and verification methodologies.
• Knowledge of analog circuit design principles and layout considerations is a plus.
• Excellent verbal and written communication skills.

Skills:

• Strong understanding of the Python language and EDA flow scripting.
• Proficiency in custom schematic/layout tools.
• Experience in RTL design and verification methodologies.
• Familiarity with analog circuit design principles.