ASIC Digital Design, Principal Engineer

Synopsys is at the forefront of technological innovation, shaping the future with advanced chip design and verification solutions. We are seeking an experienced ASIC Digital Verification Engineer to join our team and contribute to the development of high-performance silicon chips and software content.

Responsibilities:

• Design and implement verification environments for Interface IP protocols.
• Create and execute detailed test plans for complex ASIC designs.
• Develop and maintain verification IP and testbenches using SystemVerilog and UVM.
• Collaborate with design and architecture teams to identify and resolve bugs.
• Perform functional coverage analysis and drive coverage closure.
• Mentor and guide junior verification engineers in best practices.

Qualifications:

• Extensive experience in ASIC digital verification, particularly with UAL and Interface IP protocols (PCIe, CXL, DDR, Ethernet).
• Proficiency in SystemVerilog and UVM methodologies.
• Strong understanding of digital design and verification concepts.
• Experience with simulation tools like VCS or ModelSim.

Skills:

• Detail-oriented with strong analytical skills.
• Excellent communication abilities for conveying complex technical concepts.
• Collaborative team player in dynamic environments.
• Proactive and self-motivated with a commitment to continuous learning.
• Mentorship and leadership capabilities for developing junior engineers.