ASIC Floorplan Design Engineer – New College Grad 2026

NVIDIA is seeking a talented ASIC Floorplan Design Engineer, specifically targeting new college graduates, to contribute to the design and implementation of cutting-edge SoCs and GPUs. This role offers a unique opportunity to influence the development of next-generation technology across various product lines, including consumer graphics, self-driving cars, and artificial intelligence. Join a global team dedicated to pushing the boundaries of computing.

Responsibilities:

• Develop and optimize floorplans during early chip development in collaboration with architects and design leads.
• Drive the area review process and work with the ASIC design team to identify improvement opportunities in area, interconnect, and floorplan.
• Address timing and routing congestion issues by influencing early design and physical implementation decisions.
• Build tools and enhance existing infrastructure to optimize chip area and execution speed.

Qualifications:

• Master's Degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience.
• Deep hardware engineering background with a focus on VLSI and/or Computer Architecture.

Skills:

• Experience in Verilog, System Verilog, or similar hardware verification languages (HVL).
• Familiarity with CAD and physical design methodologies, including chip floorplan, power/clock distribution, packaging, P&R, and timing closure.
• Proficiency in programming languages such as Python, Perl, and C/C++.
• Strong communication and interpersonal skills, with a demonstrated ability to work effectively in a team environment.