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IC Packaging Design Engineer, Amazon Leo

Published Date: September 12, 2026
Amazon Kuiper Manufacturing Enterprises LLC, San Diego, CA
Job Description:

Amazon Leo is launching a constellation of Low Earth Orbit satellites to provide high-speed broadband connectivity to underserved communities globally. We are seeking an IC Packaging Design Engineer to join our innovative team.

Responsibilities:

  • Collaborate with digital design and RF chip designers to define floorplans, bump maps, and ball maps for beamforming ICs.
  • Work with package vendors on stack-ups, materials selection, package options, and thermal testing/design.
  • Analyze cost/performance trade-offs and complete layout of package types such as FCBGA, FCCSP, WLCSP, QFN, etc.
  • Setup and run 3D electromagnetic simulations of package + PCB using tools like HFSS and Momentum to verify designs.
  • Perform signal integrity checks and create models for packages to identify issues like crosstalk and coupling.
  • Assist the thermal team in defining and running thermal simulations of packages and PCBs.
  • Collaborate with Antenna and EE teams to design and layout test and application PCBs for packages.
  • Advise on qualification of packages: HAST, HTOL, board level reliability, etc.
  • Define and implement AI-driven workflows for packaging design, leveraging automation and machine learning.

Qualifications:

  • Bachelor's degree in Electrical Engineering or a related field.
  • 5+ years of experience in RF design, preferably in an advanced node.
  • Proven track record where products have gone to volume production.
  • Experience with RF communication systems.

Skills:

  • Master's degree in Electrical or Communications Engineering or a related field (preferred).
  • 7+ years of experience designing full-custom packages/PCBs for high performance chips (preferred).
  • Strong understanding of RF fundamentals such as s-parameters, impedance matching, and passive components.
  • Strong understanding of power integrity fundamentals, including selection and optimization of passives in package.
  • Experience routing high-speed, high pin count digital and analog interfaces (e.g., SERDES, CPU, memory).
  • Understanding of package materials properties related to high-volume production and reliability.

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