Mid-End ASIC Engineer, Senior

Positron AI is a leader in developing custom hardware systems designed to enhance AI inference performance and efficiency. We are seeking a Senior Mid-End ASIC Engineer to take charge of synthesis, timing convergence, and logical design quality for our AI accelerator roadmap. This role requires a hands-on approach to transform high-quality RTL into implementation-ready netlists while ensuring effective collaboration across various engineering teams.

Responsibilities:

• Define and own synthesis methodology for current and future ASIC generations.
• Establish signoff criteria for synthesis deliverables.
• Conduct hands-on synthesis using EDA tools like Cadence Genus and Synopsys Design Compiler.
• Develop and maintain SDC constraints and timing budgets.
• Drive logical timing closure and optimization across multiple parameters.
• Perform root-cause analysis of timing bottlenecks.
• Collaborate with architecture and RTL teams to mitigate timing risks.
• Partner with backend engineers for physical-aware optimization and timing budgeting.
• Lead cross-functional execution with various engineering teams to resolve issues rapidly.
• Serve as the synthesis technical lead with external partners, reviewing QoR and timing reports.
• Apply AI techniques to enhance timing analysis and engineering automation.

Qualifications:

• 12+ years of ASIC implementation experience with successful tapeouts.
• Expertise in synthesis methodology and flow development.
• Deep knowledge of timing closure for complex designs.
• Proficiency in Cadence Genus and/or Synopsys Design Compiler.
• Strong SDC expertise and constraint development skills.
• Understanding of RTL design principles and implementation-friendly practices.
• Hands-on experience with advanced process nodes (5nm and below).
• Strong Tcl and Python scripting skills for automation.
• Excellent debugging and root-cause analysis capabilities.

Skills:

• Synthesis methodology development
• Timing closure optimization
• SDC constraint development
• RTL design principles
• Tcl and Python scripting
• Debugging and root-cause analysis
• Collaboration and cross-functional teamwork