R&D Engineer IC Design 4

Broadcom is seeking a skilled engineer for front-end design and verification of ASIC cores. The role involves architecture definition, logic design, synthesis, and design verification through simulation and formal methods. Candidates should have a strong background in ASIC design and implementation, with the ability to work independently and collaboratively across teams.

Responsibilities:

• Define architecture and design logic blocks based on system requirements.
• Conduct synthesis and develop constraints for design blocks.
• Perform design verification through simulation and formal verification methods.
• Analyze timing from physical implementation and ensure timing closure.
• Simulate and debug designs using Verilog simulation.

Qualifications:

• BS/MS in Electrical or Computer Engineering or equivalent.
• Bachelor's degree with 8+ years of related experience, or a Master's degree with 6+ years of related experience.

Skills:

• Proficiency in TCL/Perl scripting.
• Experience with Synopsys Design Compiler/DC topo or Cadence RTL compiler for synthesis.
• Timing analysis experience with Primetime for high frequency designs.
• Understanding of liberty LIB models for timing analysis.
• Experience with formal verification tools like Synopsys Formality or Cadence Conformal.
• Familiarity with Spyglass Lint and power analysis of RTL and gate level netlists.
• Knowledge of DFT (design for test) and scan methodology.
• Version control experience with tools like SVN or Git.