Senior IC Layout design Engineer

At AMD, we harness technology to tackle the world's most pressing challenges, from healthcare advancements to AI innovations. Join us in shaping the future through cutting-edge processor design and product development, and advance your career while contributing to technology that propels the world forward.

Responsibilities:

• Design high-speed, high-performance SerDes analog mixed-signal circuits according to project specifications.
• Implement block-level physical designs, including floor-planning, power distribution, and signal routing.
• Engage in post-layout circuit performance analysis and integration activities at block/IP/chip levels.
• Estimate project schedules, track progress, and report status clearly.
• Contribute to defining layout methodologies and workflows.
• Drive initiatives for layout productivity improvements, including pcell development and automation.
• Supervise layout resources, assess layout quality, and provide feedback to design teams.

Qualifications:

• Bachelor's degree in Electrical Engineering/Computer Engineering or equivalent IC layout training with relevant experience.

Skills:

• Experience in layout design for lower process nodes (7nm or below).
• Strong understanding of analog and mixed-signal layout fundamentals, including IR, EM, capacitances, and RC delay.
• Proficient in high-speed signal routing and shielding techniques.
• Skilled in physical design verifications (LVS/DRC/ERC/ANT/ESD).
• Familiarity with circuit design concepts and IC manufacturing processes.
• Experience with high-speed SerDes blocks and PLLs in advanced Fin-FET processes is advantageous.
• Knowledge of digital integration flows and Cadence SKILL programming, as well as other languages like Perl, Python, or Tcl.
• Excellent communication skills and ability to collaborate with remote teams across different time zones.