SerDes RTL Design Engineer

At AMD, we harness technology to tackle the world's most pressing challenges, from healthcare advancements to AI innovations. Join us in shaping the future through your contributions in designing next-gen processors and leading-edge products. Together, we can advance your career and the world.

Responsibilities:

• Collaborate with system link architects to micro-architect high-speed SerDes PHY designs.
• Perform RTL design of digital blocks including calibration loops and digital signal processing.
• Apply low power design techniques and conduct PPA analysis.
• Verify functionality with block-level test benches.
• Utilize design checker tools such as LINT, CDC, and RDC.
• Conduct behavioral modeling of custom circuits using Verilog/System Verilog.
• Support functional verification, debug designs, and achieve static timing closure.
• Work with physical design and validation teams for pre-tape out sign-off and silicon bring-up.

Qualifications:

• Bachelor's or master’s degree in electrical engineering, computer engineering, or a related field.
• Proficient in logic design concepts and RTL coding using Verilog/System Verilog.
• Experience in micro-architecture and developing design specifications.
• Familiarity with design checker and functional verification tools.
• Knowledge of synthesis flow and static timing analysis.
• Understanding of low power design methodologies.
• Experience in designs with multiple clock domains.
• Background in mixed signal design.
• Proficiency in scripting languages such as Python, Perl, or TCL.
• Experience with SerDes PHY and high-speed I/O protocols is preferred.

Skills:

• Strong analytical and problem-solving skills.
• Excellent communication and teamwork abilities.
• Innovative mindset in digital design and verification.