Principal Engineer, SOC Design

Samsung Semiconductor is seeking a Principal Engineer for SOC Design within the DRAM Development Lab (DDL), part of the Memory Business Unit. This role focuses on developing silicon solutions to enhance memory and storage capabilities for emerging technologies such as machine learning and data analytics. The position requires daily onsite presence in San Jose or Folsom, California, and emphasizes collaboration with various teams to drive innovation in product roadmaps.

Responsibilities:

• Participate in architectural definitions and micro architecture of subsystem and/or chip level.
• Responsible for top integration, logic design, and RTL implementation, including quality checks (Assertion, Lint, CDC, and STA).
• Review and integrate third-party IPs, including ARM cores, DDR controllers, and UCIe PHY at the top level.
• Collaborate with architects and verification engineers to ensure sound design at the SoC level.
• Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or related field with 20+ years of experience; or a Master's degree with 18+ years; or a PhD with 15+ years of industry experience preferred.
• Hands-on knowledge and experience in ASIC design flow from design to tape out.
• Experience in ATE vector generation, testing, and silicon bring-up.
• Familiarity with commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces.

Skills:

• Strong verbal and written communication skills.
• Good understanding of PPA (performance, power, and area) trade-offs.
• Experience in SoC level synthesis, timing analysis, lint check, and CDC checks.
• Knowledge of AMBA bus fabric and ARM cores.
• Self-motivated problem-solver with teamwork capabilities.