Senior Digital ASIC Design Engineer

K2 is a pioneering space startup focused on developing the largest and most powerful satellites ever built, backed by significant investment and contracts. The company aims to revolutionize satellite technology for various missions, leveraging advancements in heavy-lift launch vehicles to create spacecraft capable of operating in extreme environments. K2 is seeking a Senior Digital ASIC Design Engineer to join their innovative team and contribute to the design of cutting-edge mixed-signal SoCs for satellite communications.

Responsibilities:

• Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog or Verilog.
• Translate algorithmic and architectural specifications into synthesizable RTL.
• Implement DSP functions such as filtering, FFT/IFFT, or beamforming.
• Convert chip specifications into RTL using internal and external IPs.
• Design and develop RTL for interfaces, power management, clocking, reset, test & debug.
• Collaborate with analog/mixed-signal teams to define digital-analog interfaces and control logic.
• Optimize designs for power, performance, and area (PPA) and support timing closure.
• Contribute to block-level integration, synthesis, and timing closure.
• Participate in design reviews, functional verification, and timing closure.
• Support chip bring-up and lab validation of complex digital subsystems.

Qualifications:

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of hands-on experience in digital ASIC design.
• Proficiency in RTL design (SystemVerilog or Verilog), synthesis, and linting tools.
• Experience in micro-architecture definition from architecture guidelines.
• Solid understanding of SoC design flows including timing constraints and formal verification.
• Familiarity with EDA tools for design, simulation, and STA.
• Experience implementing DSP functions in hardware.
• Strong debugging, problem-solving, and communication skills.

Skills:

• Experience in wireless SoC development (e.g., cellular, Wi-Fi, satellite).
• Design experience in datapath, flow control, and SoC bus architecture.
• Familiarity with DSP algorithm modeling (MATLAB, Python, or C++).
• Hands-on experience with chip bring-up and post-silicon debug.
• Knowledge of digital calibration and control of RF/mixed-signal front ends.