ASIC Design Verification Engineer

K2 is a pioneering space startup focused on developing the largest and highest-power satellites for various missions, backed by significant investment and contracts. The company aims to revolutionize satellite technology to meet the demands of a new era in space exploration, with multiple launches planned through 2026 and 2027. They are seeking a motivated ASIC Design Verification Engineer to join their team and contribute to the success of their groundbreaking projects.

Responsibilities:

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews and microarchitecture discussions.

Qualifications:

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
• Proficiency with simulation tools (VCS, Xcelium, Questa), waveform debug tools (Verdi, SimVision), and coverage tools.
• Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
• Familiarity with a scripting language (e.g., Python, Perl, TCL) and revision control systems (e.g., Git).

Skills:

• Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management.
• Familiarity with developing and integrating reference models.
• Understanding of RTL design flows and industry standard interfaces (e.g., APB/AHB/AXI).
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems is a plus.