ASIC Design Engineer [eInfochips]

eInfochips, an Arrow company, is seeking an experienced ASIC Design Engineer to join their team in Mountain View, CA. This role involves working on advanced ASIC design projects, focusing on high-speed PCIe designs and various industry-standard protocols. The ideal candidate will have a strong background in Verilog/System Verilog, EDA tools, and scripting languages, contributing to innovative product engineering and semiconductor design services.

Responsibilities:

• Proficiently code in Verilog/System Verilog.
• Utilize front-end tools including Verilog simulators and CDC checkers.
• Design high-speed PCIe interfaces and work with protocols like AXI and APB.
• Integrate ARM Fabric IPs and utilize IPXACT.
• Write scripts in Python, Tcl, and Perl for automation and efficiency.
• Employ EDA tools such as VCS, Fusion Compiler, and Design Compiler for design verification.
• Implement low power design techniques using UPF and clock crossing methods.
• Conduct Static Timing Analysis and ensure timing signoff fundamentals are met.
• Report progress to customers regularly to ensure satisfaction.

Qualifications:

• Minimum 5 years of experience in Verilog design.
• Strong understanding of RTL design and digital concepts.
• Experience with EDA tools, particularly Fusion Compiler and CDC.
• Familiarity with AMBA AXI bus and ARM or C-based processors.

Skills:

• Proficient in Verilog/System Verilog coding constructs.
• Knowledge of front-end tools and static timing analysis.
• Ability to write scripts using Python, Tcl, and Perl.
• Experience with high-speed PCIe designs and industry-standard protocols.
• Understanding of computer architecture fundamentals.