ASIC Design Verification Engineer

SHAKTECH CORP is seeking an experienced ASIC Design Verification Engineer for a remote contract position. The ideal candidate will have 12 years of experience and will play a crucial role in verifying the functionality and performance of custom silicon designs.

Responsibilities:

• Develop and execute verification plans for block, subsystem, and full-chip environments.
• Build SystemVerilog/UVM test benches including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification into the design process.
• Drive constrained-random and directed testing strategies to ensure thorough verification.
• Run simulations, triage failures, and collaborate closely with RTL designers to resolve issues.
• Implement and maintain coverage models for design sign-off.
• Manage regression testing, CI pipelines, and simulation farms to ensure continuous integration and testing.
• Participate in design reviews and microarchitecture discussions to provide insights and feedback.

Qualifications:

• 12 years of experience in ASIC design verification.
• Strong understanding of RTL design flows and industry-standard interfaces such as APB, AHB, and AXI.

Skills:

• Proficiency in SystemVerilog and UVM for test bench development.
• Experience with writing SystemVerilog Assertions (SVA).
• Ability to drive both constrained-random and directed testing strategies.
• Strong simulation and debugging skills to triage failures effectively.
• Familiarity with managing CI pipelines and regression testing environments.