Staff ASICS Physical Design Engineer

Qualcomm Technologies, Inc. is seeking a highly skilled individual to lead and perform timing analysis for complex sub-systems within the Engineering Group, specifically in ASICS Engineering. This role involves synthesizing ambiguous requirements and ensuring timing closure across various operating modes for premium tier chips utilizing advanced technology nodes such as 14nm, 5nm, 34nm, and 3nm.

Responsibilities:

• Lead timing analysis of complex sub-systems in System-on-Chips (SoC) context.
• Ensure timing closure across various operating modes and corners.
• Perform constraint validation at different design stages.
• Conduct clock tree analyses and early planning of pipelines for critical interface timing closure.
• Develop multiple flows/scripts for easy access to timing reports.
• Mentor and train junior team members.
• Perform correlation activities between PNR tools and timing signoff tools.
• Generate Engineering Change Orders (ECOs) for various subsystems.
• Contribute actively in design reviews and project meetings.
• Communicate and implement development plans.

Qualifications:

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Seven years of progressive experience in a related occupation.

Skills:

• Expertise in SoC design architecture and methodologies.
• Advanced knowledge in timing analysis and timing signoff processes.
• Proficiency in developing scripts and flows for timing reports.
• Strong analytical and problem-solving skills.
• Excellent communication and mentoring abilities.