Published Date: June 25, 2026
Spanidea Inc, San Jose, CA
Job Description:
We are seeking an experienced IC CAD/Design Methodology Engineer to manage and optimize advanced foundry PDKs for cutting-edge FinFET technologies. This role involves developing and supporting Cadence-based design flows, establishing verification methodologies, and driving automation to enhance design productivity.
Responsibilities:
- Manage, qualify, and maintain advanced foundry PDKs for FinFET technologies (2nm/3nm/5nm).
- Develop, optimize, and support end-to-end Cadence-based design flows for various design types.
- Establish and maintain physical verification and signoff methodologies using Calibre and StarRC.
- Support advanced reliability verification, including EMIR analysis and electrical rule checking.
- Drive flow automation, scripting, and tool integration to improve design productivity.
- Collaborate with design teams, foundries, and EDA vendors to resolve technical challenges.
Qualifications:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
- 5+ years of hands-on IC CAD/Design Methodology experience in advanced semiconductor technologies.
Skills:
- Strong experience with advanced-node FinFET processes (5nm, 3nm, or 2nm).
- Deep expertise with Siemens Calibre, Synopsys StarRC, and Cadence Virtuoso/Innovus.
- Strong scripting skills in SKILL and Perl, with knowledge of Python, Tcl, and Shell scripting.
- Solid Linux experience, including compute cluster/grid environments and version control systems.
