ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead [Remote]

Cisco is seeking a Signal and Power Integrity Technical Lead for its Hardware Engineering team in San Jose, CA, with remote options available for U.S. residents. The role focuses on developing next-generation ASIC packaging for Cisco's innovative hardware platforms, which are central to the AI era and power core Switching, Routing, and Wireless products globally. The Common Hardware Group (CHG) is known for its cutting-edge silicon and hardware innovations, including the Cisco Silicon One architecture, which drives complex networks and carries a significant portion of global IP traffic.

Responsibilities:

• Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
• Analyze substrate signal integrity (SI) and power integrity (PI), collaborating with the layout team to optimize solutions across interposer, substrate, and PCB.
• Design and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
• Collaborate with system partners, vendors, and design leads to resolve complex technical issues and achieve combined power and signal integrity.
• Define processes, methods, and tools for complex ASIC/package developments.
• Lead discussions on chip architecture and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal designs.
• Mentor junior engineers and support the signal integrity team, ensuring technical specifications are met.
• Promote a culture of design reviews, postmortems, and continuous improvement across engineering teams.

Qualifications:

• Bachelor's degree in Electrical Engineering with 8+ years of relevant experience, or a Master's degree with 6+ years, or a PhD with 3+ years in signal and power integrity.
• Expertise in high-speed design principles, including Transmission Line Theory and impedance network analysis, particularly for 56G PAM4 SerDes architectures.
• Experience with pre- and post-layout SI/PI simulations using EDA tools like Cadence Sigrity and Ansys HFSS.
• Experience conducting layout reviews and physical design validation using Cadence APD and Ansys EM flows.
• Working knowledge of SPICE for circuit-level analysis and signal modeling.

Skills:

• Strong communication skills to articulate technical concepts to diverse audiences.
• Proficiency in high-speed memory interface SI and die-to-die interfaces (UCIe or proprietary).
• Experience with advanced packaging techniques such as CoWoS and EMIB.