Principal ASIC Engineer [Reliability & Hardware Validation] Hybrid

Cisco is seeking a highly skilled Engineer to lead reliability and hardware design validation for next-generation semiconductor and networking products in a hybrid role based in San Jose, California. This position is part of the Cisco Hardware Engineering Team, which focuses on developing innovative hardware solutions that adhere to industry standards and enhance user experience.

Responsibilities:

• Define and execute comprehensive product/process qualification plans for high-power solutions.
• Drive robust HTOL, Burn-In, and stress testing, managing reliability suppliers to meet qualification schedules.
• Lead hardware design, schematic generation, and validation for service provider routing products.
• Conduct failure analysis and generate detailed qualification reports to ensure product integrity.
• Collaborate with eCAD, FPGA, Power, Mechanical, Signal Integrity, and Manufacturing teams for design-for-reliability and compliance.
• Provide technical documentation and support for customer quality and reliability requirements.

Qualifications:

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of professional experience in semiconductor reliability and/or high-speed hardware design.
• Proven experience in developing high-power HTOL/Burn-In testing for advanced node products.
• Hands-on experience with high-speed network interfaces and board design.

Skills:

• Deep knowledge of JEDEC, AEC, and Telcordia standards.
• Experience with high-speed measurement equipment and automated test development.
• Proficiency in data analysis/debug and HTOL set-up.
• Familiarity with tools such as Cadence Allegro.