When a semiconductor device fails, the visible damage is not necessarily the root cause. A damaged metal line, cracked package, leaking transistor or burned bond wire may be the final result of a sequence of events rather than the original problem. The purpose of the semiconductor failure analysis process is therefore to move systematically from the observed failure to its physical mechanism and ultimately to its root cause.
A typical IC failure analysis workflow may include:
The exact sequence varies depending on the semiconductor technology, package, failure mode and information already available. In most cases, however, one principle is especially important:
Start with the least invasive techniques and progressively move toward more localized and destructive analysis.
This helps preserve evidence and reduces the risk of destroying the actual failure before it has been understood.
For a broader introduction to the subject, see:
Semiconductor Failure Analysis: The Complete Guide to IC Failure Analysis
For a detailed comparison of analytical methods, see:
IC Failure Analysis Techniques: A Complete Guide
| Step | Objective | Typical Methods | Expected Result |
|---|---|---|---|
| Failure information | Understand the device and failure history | Documentation, test data, application information | Initial failure hypothesis |
| Failure verification | Confirm that the reported failure exists | Functional test, electrical test | Reproduced failure |
| Electrical characterization | Understand how the device fails electrically | I-V measurements, curve tracing, current measurements | Electrical failure signature |
| Non-destructive inspection | Look for package or structural abnormalities | Optical inspection, X-ray, SAM | Potential defect identified |
| Fault localization | Narrow the failure to a physical region | EMMI, OBIRCH, thermal analysis, nanoprobing | Region of interest identified |
| Sample preparation | Expose the area requiring investigation | Decapsulation, delayering, cross-sectioning | Accessible failure site |
| Physical analysis | Identify the physical defect | SEM, FIB, TEM | Physical defect observed |
| Material analysis | Determine composition or structure | EDS/EDX, TEM and other analytical methods | Material or structural evidence |
| Failure mechanism | Explain how the device physically failed | Correlation of electrical and physical evidence | Failure mechanism identified |
| Root cause | Determine why the failure occurred | Design, process, packaging and application review | Root cause established |
| Corrective action | Prevent recurrence | Process, design, test or application changes | Verified improvement |
A semiconductor failure analysis process is a structured investigation used to determine why an integrated circuit or semiconductor device does not perform as expected. The analysis attempts to connect several different levels of information:
Observed failure
↓
Electrical failure signature
↓
Failure location
↓
Physical defect
↓
Failure mechanism
↓
Root cause
↓
Corrective action
This distinction is important. For example, imagine an integrated circuit that exhibits excessive supply current. The excessive current is the failure symptom.
Electrical analysis may localize the abnormal current to a specific circuit block. Emission microscopy may then identify a small region producing abnormal light emission. FIB and SEM analysis may reveal a short between two interconnect structures.
The short is the physical defect. Further analysis might determine that the short resulted from a manufacturing particle. The contamination event that created the particle may ultimately be identified as the root cause.
Successful semiconductor failure analysis therefore requires more than identifying damaged material. The objective is to explain why the damage occurred.
A good failure investigation starts before the semiconductor device enters the laboratory. The analyst should collect as much information as possible about the device, the failure and the environment in which the failure occurred.
Useful information may include:
One of the most useful questions is: What happened immediately before the device failed?
For example:
These details can strongly influence the analysis strategy. A single random failure may require a different investigation from dozens of devices showing exactly the same failure signature.
One of the biggest risks in failure analysis is accidentally altering or destroying evidence. Before sending the device for analysis, avoid unnecessary:
unless these actions are part of a controlled analysis plan. Once a physical feature has been removed or altered, the original condition may be impossible to reconstruct. This is why the failure-analysis workflow normally begins with documentation and non-destructive analysis before progressing toward invasive techniques.
The next step is to confirm that the reported failure can actually be reproduced. This may sound obvious, but it is extremely important.
If the laboratory cannot reproduce the failure, the problem may be:
The device may therefore be tested under conditions that reproduce the original operating environment as closely as practical.
Testing may include:
A known-good device can be extremely valuable at this stage. Comparing a failing device with a good device can reveal differences that might otherwise be difficult to identify.
Failure verification answers:
“Does the device actually exhibit the reported failure?”
Failure analysis answers:
“Why does the device exhibit that failure?”
The first should normally be established before destructive investigation begins.
Once the failure has been reproduced, engineers attempt to understand its electrical behavior. This stage is commonly called Electrical Failure Analysis (EFA).
The objective is to create an electrical signature of the problem. Depending on the device, engineers may investigate:
Electrical characterization helps narrow the search.
For example, instead of knowing only that:
“The IC does not work,”
the analyst may determine that:
“The device has excessive leakage between two supply domains when a particular block is enabled.”
That is a much more useful starting point for fault localization.
Read more:
Electrical Failure Analysis (EFA) of Integrated Circuits
Before opening or cutting the semiconductor package, non-destructive analysis should normally be considered. The exact methods depend on the suspected failure.
External inspection may reveal:
X-ray inspection can provide information about structures hidden inside the package.
It may reveal:
Read more:
X-Ray Inspection of Semiconductor Packages
Scanning Acoustic Microscopy, or SAM, is particularly useful for investigating interfaces within semiconductor packages.
It can help identify:
Read more:
Scanning Acoustic Microscopy for IC Package Analysis
These techniques can provide important information while leaving the semiconductor device available for additional investigation.
After establishing the electrical failure signature, one of the most important objectives is determining where the failure is located.
An advanced IC may contain millions or billions of structures. Physically examining the entire device at high resolution would be impractical. The analyst therefore attempts to progressively narrow the search area.
This process is called:
Possible techniques include:
The goal is to identify a Region of Interest (ROI) for subsequent physical analysis. A successful fault-localization result might reduce the investigation from an entire die to:
The smaller the region of interest becomes, the more efficiently physical analysis can be performed. For more information about individual methods, see: IC Failure Analysis Techniques: A Complete Guide
Once the failing region has been sufficiently localized, physical access to the semiconductor may be required. For packaged devices, this can involve IC decapsulation.
Decapsulation removes package material so that the die can be inspected or analyzed. Depending on the package and investigation, the sample may subsequently require:
Sample preparation is a critical part of the failure-analysis process. A sophisticated microscope cannot provide useful information if the wrong area has been exposed or if the preparation process destroys the defect.
Read more:
IC Decapsulation: Methods, Process and Applications
Once the area of interest has been exposed, engineers can begin detailed Physical Failure Analysis (PFA).
The objective is to determine what physical abnormality exists in the location identified during electrical analysis.
Common techniques include:
The investigation might identify:
Physical analysis and electrical analysis are complementary rather than competing approaches. Modern semiconductor FA workflows use both to localize electrical abnormalities and then examine their physical origin.
Read more:
Physical Failure Analysis (PFA) of Semiconductor Devices
Scanning Electron Microscopy provides high-resolution images of semiconductor structures.
SEM can be used to examine:
Read more:
SEM Analysis for Semiconductor Failure Analysis
Focused Ion Beam analysis is especially useful when a defect is buried below the surface. FIB can precisely remove material from a selected region.
Applications include:
AnySilicon already has dedicated content covering:
and
Transmission Electron Microscopy may be required when the suspected defect is too small or structurally complex for conventional SEM analysis.
TEM can provide detailed information about:
The site of interest is commonly prepared as a very thin sample using FIB before TEM examination.
Finding an abnormal structure does not always explain what it is. Consider a particle found between two metal lines. SEM may reveal the particle’s size and location, but additional analysis may be necessary to determine its composition.
Techniques such as EDS/EDX can help determine which elements are present. This can support investigations involving:
Other sophisticated materials-analysis techniques may be required depending on the semiconductor technology and the problem being investigated. For extremely small or complex structures, advanced electron microscopy and other nanoscale characterization methods can be required.
At this point the investigation may have identified a physical defect. The next question is:
How did this defect cause the device to fail? This is the failure mechanism.
Examples of semiconductor failure mechanisms include:
The distinction between a physical observation and a failure mechanism is important.
For example:
Observation: A metal line is open.
Mechanism: Electromigration created a void until electrical continuity was lost.
But even this may not yet be the root cause.
Root-cause analysis asks:
Why did the failure mechanism occur?
Continuing the electromigration example:
Failure symptom: Circuit stops operating.
↓
Electrical failure: Open circuit.
↓
Physical defect: Void in metal interconnect.
↓
Failure mechanism: Electromigration.
↓
Possible root cause: Excessive current density caused by a design condition.
The failure mechanism and root cause are therefore not necessarily the same thing.
Another example:
Failure symptom: Excessive leakage.
↓
Physical defect: Damaged gate oxide.
↓
Failure mechanism: Electrical overstress.
↓
Possible root cause: System-level voltage transient exceeding the IC rating.
A strong failure-analysis report should therefore distinguish:
The strongest root-cause conclusions normally come from multiple pieces of evidence that support the same explanation.
This might include:
The more independent evidence supports the same explanation, the stronger the root-cause conclusion becomes.
Failure analysis does not always produce a definitive root cause. Sometimes the original defect has been destroyed by the failure itself.
Sometimes there is insufficient material remaining. Sometimes only one sample is available.
Sometimes the electrical failure cannot be reproduced. A technically sound FA report should clearly distinguish between:
A plausible explanation should not be presented as proven unless the evidence supports it.
Finding the root cause has limited value unless the information is used to reduce the chance of recurrence. Corrective action depends on where the problem originated.
Examples might include:
Examples might include:
Examples might include:
Examples might include:
Examples might include:
Corrective action should ideally be verified rather than assumed to have solved the problem. Verification may involve:
This closes the failure-analysis loop. The complete process therefore becomes:
Failure
↓
Analysis
↓
Root cause
↓
Corrective action
↓
Verification
↓
Improved reliability
Consider an IC returned from a customer because of unexpectedly high supply current.
Electrical testing confirms that the returned IC consumes significantly more current than known-good units.
I-V measurements show an abnormal low-resistance path between two power domains.
X-ray and package inspection reveal no obvious package problem.
Emission microscopy identifies an abnormal emission region on the die.
The package is opened while preserving the relevant die region.
FIB is used to expose the suspected interconnect area.
SEM reveals a physical bridge between neighboring structures.
Additional analysis identifies unexpected material associated with the bridge.
The bridge created an electrical short between the structures.
Manufacturing data are reviewed to determine where the contamination or defect may have been introduced.
The relevant process step is modified.
Subsequent devices are tested to confirm that the failure no longer occurs. This example demonstrates why semiconductor failure analysis is not simply one laboratory test. It is a chain of evidence.
Immediately cutting, grinding or opening the device may destroy useful evidence.
Whenever practical, complete relevant non-destructive analysis first.
A visible damaged area may be secondary damage rather than the original failure.
Electrical localization can help avoid this mistake.
“EOS” or “electromigration” may describe how the device failed, but not necessarily why it happened.
The investigation should attempt to determine the condition that initiated the failure mechanism.
Some IC failures originate outside the semiconductor itself.
PCB conditions, power supplies, thermal conditions and system transients may all be relevant.
A known-good unit can significantly improve electrical and physical comparisons.
One unusual feature does not automatically prove root cause.
Conclusions should ideally be supported by multiple independent observations.
Failure analysis is not limited to customer returns. It can also support semiconductor manufacturing and yield improvement. For example, wafer-sort results may show repeated failures at a particular die location or circuit function.
A typical investigation could include:
Test-data analysis
↓
Selection of representative failing dies
↓
Electrical characterization
↓
Fault localization
↓
Physical analysis
↓
Correlation with wafer/process data
↓
Identification of process-related root cause
This type of analysis can help engineers connect electrical yield loss with physical manufacturing defects.
Failure analysis is also important when devices fail qualification or accelerated reliability testing.
Examples include:
The FA process helps determine whether the observed failure represents:
Understanding the failure mechanism is essential before deciding what corrective action is appropriate.
Advanced semiconductor technologies increasingly require sophisticated combinations of electrical localization, sample preparation and high-resolution characterization.
For small or deeply buried defects, a workflow can involve:
Electrical Failure Analysis
↓
Nanoprobing or other fault-localization techniques
↓
FIB cross-section / sample preparation
↓
SEM
↓
TEM
This reflects an important principle in modern FA: The more complex the device becomes, the more important precise localization becomes before destructive analysis begins.
The first step should normally be collecting information about the device and failure history, followed by confirming that the failure can be reproduced.
Physical analysis should not begin until the failure has been sufficiently characterized.
Failure analysis investigates what failed and how it failed.
Root-cause analysis goes further and attempts to identify the underlying reason the failure occurred.
Root-cause analysis is therefore usually part of the broader failure-analysis process.
Electrical analysis helps characterize and localize the failure.
Without localization, physical analysis may involve searching a very large semiconductor structure without knowing where the relevant defect is located.
No.
Electrical characterization, optical inspection, X-ray and acoustic microscopy can often be performed without destroying the sample.
Techniques such as decapsulation, cross-sectioning, FIB milling and TEM preparation can be invasive or destructive.
A complete investigation may provide:
The exact level of conclusion depends on the available evidence.
There is no standard duration.
A straightforward package-related investigation may require relatively few analytical steps, while a difficult transistor-level problem could involve multiple iterations of electrical localization, FIB, SEM and TEM.
The availability of samples and the ability to reproduce the failure can also affect the investigation.
A successful semiconductor failure analysis investigation does not begin with the most powerful microscope available.
It begins with the failure itself.
The most effective workflow progressively converts an unknown problem into increasingly specific information:
The IC fails
↓
The electrical behavior is characterized
↓
The failure is localized
↓
The physical defect is identified
↓
The failure mechanism is established
↓
The root cause is determined
↓
Corrective action is implemented
This systematic approach reduces unnecessary analysis, protects valuable evidence and increases the likelihood of identifying a meaningful root cause.
If you have a failed semiconductor device, IC, wafer or package, AnySilicon can help connect you with companies providing semiconductor failure-analysis services.
Requirements may include:
Find a Semiconductor Failure Analysis Company
When requesting support, provide as much information as possible about the failed device, package type, observed failure, available samples and analysis already performed. This can help identify the most appropriate laboratory and analysis workflow.