ASIC Design Engineer 2

Hewlett Packard Enterprise (HPE) is seeking an ASIC Design Engineer 2 to join their Juniper Silicon group, focusing on the design of advanced networking chips. This role is primarily onsite and offers a dynamic environment where innovation and teamwork are emphasized. HPE values diverse backgrounds and provides opportunities for personal and professional growth.

Responsibilities:

• Develop detailed micro-architecture specifications from functional specifications with guidance from senior engineers.
• Perform RTL coding, preferably in System Verilog, and engage in coding projects.
• Write functional coverage and System Verilog Assertions (SVA) with training provided if necessary.
• Collaborate with Physical Design (PD) teams to identify and resolve timing issues in RTL to meet frequency targets.
• Debug issues identified by the verification team using state-of-the-art EDA tools.

Qualifications:

• Bachelor’s degree in Electrical Engineering required; Master’s degree strongly desired.
• Completion of courses in digital logic design is essential.
• Strong analytical and problem-solving skills.

Skills:

• Proficient coding skills in Verilog/System Verilog through academic and internship projects.
• Knowledge of computer architecture, networking protocols, and machine learning is a plus.
• Familiarity with Perl/Python is advantageous.
• Excellent written and verbal communication skills.