DFT Engineer – Semiconductor / ASIC / SoC

We are seeking a skilled DFT Engineer with over 5 years of experience in Design-for-Test (DFT) for semiconductor ASIC/SoC designs. The position is based in the Bay Area, California, and requires onsite work from day one. The role involves collaboration with various engineering teams to enhance DFT methodologies and improve test coverage.

Responsibilities:

• Design, implement, and verify DFT/DFx features for ASIC/SoC designs.
• Perform DFT verification and validation activities.
• Support ATPG generation, analysis, debugging, and test coverage improvement.
• Work extensively with IEEE 1687 / IJTAG, ICL, and PDL.
• Debug DFT and test-related issues and drive resolution with cross-functional teams.
• Analyze test results and identify opportunities to improve test coverage and quality.
• Collaborate with RTL, design, verification, and test teams throughout the DFT lifecycle.
• Support DFT/test methodologies, verification flows, and production-quality deliverables.

Qualifications:

• 5+ years of hands-on DFT/DFx Engineering experience
• Strong experience in DFT Verification
• Hands-on experience with ATPG
• Strong knowledge of IEEE 1687 / IJTAG
• Experience with ICL (Instrument Connectivity Language)
• Experience with PDL (Procedural Description Language)
• Experience with ASIC/SoC semiconductor designs
• Strong debugging and problem-solving skills
• Experience with DFT/test methodologies and flows

Skills:

• Experience with commercial DFT tools
• Siemens Tessent experience (preferred)
• Experience working on complex ASIC/SoC designs
• Strong understanding of semiconductor DFT verification methodologies