Category Archives: ASIC Design

Faraday Continues Expanding Its Ethernet Solutions for Networking Demands in ASIC

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Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, announced that its Gigabit Ethernet PHY has been silicon proven on UMC’s 28HPC+ process and is now available for new ASIC SoC designs and IP licensing. This new IP, based on 28nm node, provides the benefits of

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Faraday Launches Cortex-A53-based Platform to Accelerate FinFET SoC Development

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Faraday Technology Corporation (TWSE: 3035), leading ASIC design service and IP provider, today launched SoCreative!VI™ A600 SoC development platform implemented in Samsung Foundry’s 14LPP FinFET process technology. This platform is equipped with Faraday’s A600 SoC chip on an evaluation board and the Linux software development kit (SDK) to create a full-performance system

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Introduction to Physical Design

There are numerous steps that are involved in the design of digital (or mixed signal) circuits starting from system specifications right till the chip is manufactured. One of these steps is a process of transforming a functionally described circuit (normally in netlist) into physical layout at the lowest level (normally

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The Ultimate Guide to Power Gating

power gating

Power gating is a technique used to reduce ASIC and SoC power consumption by turning off parts of the design that are not being used or in inactive mode. Also, it is a very efficient technique to reduce leakage power in ASIC designs.
 
The basic concept is to have

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Sondrel explains the vital coordinating role of Systems Architects

Reading, UK  11 January 2021. Leading edge digital ASIC design becomes more complex every year needing teams of dozens of people working on all the different aspects of it. According to Sondrel, who specialises in these advanced chip designs, there is a growing need for Systems Architects who coordinate every

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SoC Development Overview

This article focuses on the various stages of SoC development. In a typical SoC development, there are many steps that are highly dependent and linked to each other. SoC design flow works on multiple optimization goals and constraints and therefore requires various SoC development skills and EDA tools.
 
What

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