Leuven, March 1st 2024 – “In February 2004, we started ICsense with a team of 4 people and today ICsense employs over 100 dedicated chip experts”, says CEO Bram De Muer. “We’re really proud to have the best fab-independent European IC design team with world-class expertise in analog, digital, mixed-signal and high-voltage design.
Read MoreThis interview was held with Ravishankar Balasubramanian, CEO of BLR LABS Pvt Ltd.
Q : Tell me a bit about your background? How did you first get started with BLR LABS?
Thank you for asking me that question. Personally speaking, I come from a challenging background
Faraday Technology Corporation (TWSE: 3035), a leader in ASIC design services and IP solutions, announces its collaboration with Arm and Intel in spearheading the development of a 64-core System-on-Chip (SoC) utilizing Intel 18A technology. This innovative SoC seamlessly integrates Arm® Neoverse™ Compute Subsystems (CSS), delivering unparalleled performance and power efficiency
Read MoreMILPITAS, CALIFORNIA, UNITED STATES, January 31, 2024 — Marquee Semiconductor, a global leader in chip design solutions, announces it has brought on semiconductor industry veteran Gideon Intrater as a Strategic Advisor. Mr. Intrater brings to Marquee more than 30 years of experience gained through technical, marketing and sales leadership roles at
Read MoreTransaction brings Cadence skilled system design expertise in delivering end-to-end custom solutions to customers across multiple industries
SAN JOSE, Calif.– January 08, 2024 — Cadence Design Systems, Inc. (Nasdaq: CDNS) announced today that it has acquired Invecas, Inc., a leading provider of design engineering, embedded software and system-level solutions, headquartered
Design for Testability (DFT) engineer is an indispensable cornerstone within the semiconductor industry, providing a vital framework that ensures the reliability, efficiency, and cost-effectiveness of integrated circuits. Its primary objective revolves around embedding testability features directly into the design phase of these intricate circuits, thereby facilitating streamlined testing procedures, early
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