Category Archives: ASIC Design

SiPearl and Open-Silicon Research Collaborate to Accelerate Custom Silicon for High Performance Computing (HPC) Applications

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MAISONS-LAFFITTE, France – February 23, 2021 SiPearl, the company designing the high-performance, energy-efficient microprocessor for the European exascale supercomputer and Open-Silicon Research, the India based entity of OpenFive, a leading provider of custom silicon solutions with differentiated IP, today announced a multi-year joint collaboration to enable expansive development of innovative

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The Ultimate Guide to Clock Gating

Clock Gating is defined as: “Clock gating is a technique/methodology to turn off the clock to certain parts of the digital design when not needed”.
 
The Need for Clock Gating
 
With most of the SoCs heavily constrained by power budgets, it is of utmost importance to reduce power

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HDL Design House Partners with Marketing Platform AnySilicon

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AnySilicon, the leading marketplace for ASIC service providers, announced today that HDL Design House, a leading-edge digital, analog, and back-end design and verification services provider, has joined AnySilicon to promote its design services. As part of the AnySilicon platform, HDL Design House will gain access to a full range of

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Protocol and Interface Agnostic Universal D2D Controller for HPC and Chiplets

Demand for die-to-die and chip-to-chip interfaces has been growing steadily in the past few years due to new applications in cloud/data centers, AI (training and edge applications), and High-Performance Computing (HPC). The demand is driven by the requirements of high throughput, low latency and low power in these applications. Advances in packaging technology are further helping the

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The Ultimate Guide to Static Timing Analysis (STA)

static timing analysis (STA)

Static Timing Analysis is defined as: a timing verification that ensures whether the various circuit timing are meeting the various timing requirements.
 
One of the most important and challenging aspect in the ASIC/FPGA design flow is timing closure. Timing closure can be viewed as timing verification of the digital

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Sondrel explains the secret of big digital chip design is all in the NoC

Sondrel is known for designing very large digital chips and the secret to lies in its ability to ensure that data flows around the chip between blocks correctly using a Network on Chip (NoC). Without a NoC, a chip could need up to ten times more memory to operate in

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