Category Archives: Blog

Amkor Delivers Industry’s First Package Assembly Design Kit to Support Mentor’s High-Density Advanced Packaging Tools

July 21, 2018, anysilicon

Amkor Technology announced today it has partnered with Mentor to release Amkor’s SmartPackage™ Package Assembly Design Kit (PADK), the first in the industry to support Mentor’s High-Density Advanced Packaging (HDAP) design process and tools. Amkor’s award-winning High-Density Fan Out(HDFO) process can now be used in conjunction with Mentor’s software to deliver

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HDL Design House and Mentor Workshop at Aviation Electronics Europe 2018

May 24, 2018, anysilicon

HDL Design House, provider of digital, analog, and back-end design and verification services and products in numerous areas of SoC, will host a joint technical workshop with Mentor, a Siemens business, at the Aviation Electronics Europe conference on June 19th, 2018 at the MOC Event Center in Munich, at 4pm.

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Dolphin Integration Joins GlobalFoundries FDXcelerator™ Program to Provide Breakthrough Fabric IP

October 17, 2017, anysilicon

Energy management is at the heart of the new generation of systems-on-chips (SoCs) targeting battery-powered applications. More complex power architectures are required to enable devices to run on the same battery for years rather than months. These new architectures often result in new noise challenges.
 
To deal with the

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Rohde & Schwarz America and DA-Integrated Collaborate on IC Tester for Advanced RF & Millimeter Wave Integrated Circuits

May 17, 2017, anysilicon

COLUMBIA, Md., May 9, 2017 /PRNewswire/ — Rohde & Schwarz America (RSA), a leading supplier of test & measurement equipment, and DA-Integrated, a company that offers advanced production test systems for development, characterization and volume production, have announced today that they have collaborated to develop an on-wafer RFIC production test

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Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production

April 02, 2016, anysilicon

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its digital, signoff and custom/analog tools have achieved V1.0 Design Rule Manual (DRM) and SPICE certification from TSMC for its 10-nanometer (nm) FinFET process. Cadence and TSMC are also continuing to collaborate on the advancement of 7nm technologies and have completed

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ASIC Design Flow – an Overview

August 07, 2014, anysilicon

Today, ASIC design flow is a very solid and mature process. The overall ASIC design flow and the various steps within the ASIC design flow have proven to be both practical and robust in multi-millions ASIC designs until now.
Each and every step of the ASIC design flow has a

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