Category Archives: IP Cores

Aldec and Tamba Networks Release Ultra Low Latency Ethernet Solution for UltraScale+ FPGA at The Trading Show 2018

text labeled PRESS RELEASE

Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has utilized Aldec’s HES-XCVU9P-QDR UltraScale+ board with Tamba Networks 10G Ethernet MAC IP Core to deliver a proven Ultra-Low Latency (ULL) Ethernet solution that provides ~56ns roundtrip Ethernet latency using QSFP28 channels.
 
“High

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GLOBALFOUNDRIES Choose INNOSILICON as Cooperative Partner

Partnership

Innosilicon is proud to announce the expansion of our IP portfolio into GLOBALFOUNDRIES new 22nm FDX technology node. Innosilicon’s IP in 22FDX offers an excellent combination of performance, power consumption and ease of use that Innosilicon is known for.
 
“We have worked closely with GlobalFoundries for years to ensure

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T2M announces availability of Bluetooth SIG qualified v5 Bluetooth Low Energy Controller, Stack and Profiles IP from Mindtree

T2M, the world’s largest independent global semiconductor technology provider, announced the availability of Mindtree’s BQB (Bluetooth Qualification Body) qualified Bluetooth v5 Controller, Stack and Profiles (Declaration ID #D038059 and #D038060). This makes Mindtree the first company to qualify a full featured Bluetooth Low Energy 5 IP with TCRL 2 Specifications.

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Understanding Bluetooth Mesh – the Next Wave of IoT Technology

Launch.

The market for Bluetooth low energy devices is expected to reach 1.4 Billion, growing at a CAGR of 34% between 2015 to 2021, as per ABI Research. While investments in Internet-of-Things (IoT) technology are ever increasing, there are many wireless technologies such as Zigbee, Wi-Fi, Bluetooth and Z-wave competing for

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Dolphin Integration augments the TSMC IP Ecosystem at 40 nm ULP eFlash with new TITAN Read Only Memory

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Dolphin Integration, leader in innovative design solutions for the next generation of Energy-Efficient System-on-Chips, augments TSMC’s IP ecosystem at 40 nm with TITAN, a breakthrough architecture for Read Only Memory compiler. This cost effective, single-layer and late programmable ROM compiler is capable of generating instance sizes from 512 bits to

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Codasip Welcomes Jerry Ardizzone to Executive Team as Vice President of Worldwide Sales

Codasip, the leading supplier of RISC-V® embedded processor intellectual property, today announced that Jerry Ardizzone has joined as Vice President of Worldwide Sales, reporting to CEO Karel Masařík.
 
“We are very excited to have Jerry on board to lead our global sales efforts,” declared Karel Masařík, CEO and founder

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