ASIC Design Engineer

Positron AI is at the forefront of developing custom hardware systems designed to enhance AI inference capabilities, offering superior performance and efficiency compared to traditional GPU systems. The company is dedicated to creating the best AI inference systems globally.

Responsibilities:

• Define and document microarchitecture for complex IP blocks/subsystems.
• Deliver production-quality, parameterized SystemVerilog RTL with well-defined interfaces and embedded assertions.
• Lead lint, CDC/RDC, DFT integration, and synthesis bring-up; collaborate with physical design on floorplan and timing closure.
• Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets.
• Architect and integrate high-performance interconnects, DMA engines, coherency logic, and high-speed memory interfaces.
• Engage with IP vendors and internal stakeholders for seamless integration.
• Develop and enforce coding guidelines, reusable IP packaging, and signoff checklists.
• Contribute automation flows to improve team efficiency.
• Partner with Verification to define test plans and reference models.
• Work with Architecture and Performance teams to correlate models against RTL.
• Support bring-up, post-silicon debug, and customer engagements as required.
• Guide junior engineers in design techniques and problem-solving.
• Lead design reviews and advocate for best-in-class solutions.

Qualifications:

• BS/MS in Electrical Engineering/Computer Engineering or related field with 8+ years of ASIC/SoC RTL design experience.
• Proven track record of leading designs from specification to RTL signoff with strong PPA outcomes.
• Deep expertise in SystemVerilog RTL, including clocking, resets, and protocol correctness.
• Extensive experience with front-end flows/tools using major EDA suites.
• Hands-on expertise with HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, and high-throughput datapaths.
• Strong cross-functional communication skills.

Skills:

• Expertise in AI/ML accelerator design and low-power design techniques.
• Formal verification/SVA expertise for property checking and design assertions.
• Collaboration experience with cocotb/UVM for checkers and reference model co-development.
• Familiarity with RISC-V subsystems and coherence protocols.