ASIC Engineer, SoC Verification

Meta is seeking an experienced ASIC Design Verification Engineer to join its Infrastructure organization. This role involves working on the design verification of IP and System On Chip (SoC) for data center applications, focusing on developing innovative ASIC solutions. The engineer will collaborate with cross-functional teams to ensure high-quality designs and achieve verification closure through various methodologies.

Responsibilities:

• Define and implement IP/SoC verification plans and build verification test benches.
• Develop functional tests based on the verification test plan.
• Drive Design Verification to closure based on defined metrics, including functional and code coverage.
• Debug and resolve functional failures in collaboration with the Design team.
• Work with cross-functional teams to ensure the highest design quality.
• Implement continuous improvements in Design Verification using the latest methodologies and tools.

Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
• 8+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
• 8+ years of experience in IP/sub-system and/or SoC level verification using SystemVerilog UVM/OVM methodologies.
• Experience with functional verification, SV Assertions, Formal, and Emulation.
• Proficiency in EDA tools and scripting languages (Python, TCL, Perl, Shell).
• Experience in architecting and implementing Design Verification infrastructure.

Skills:

• Expertise in SoC Level verification for CPU, GPU, or AI accelerator architectures.
• Experience leading the full verification cycle of SoC or complex sub-systems.
• Familiarity with Emulation, Firmware, and Post-Silicon Validation.
• Knowledge in Chip Debug, Boot, CPU Subsystems, PCIe, NIC, and Memory Subsystems.
• Ability to develop System level use-cases and End-to-end tests at SoC level.