ASIC Physical Design Engineer, Principal

Positron AI is at the forefront of developing next-generation AI inference accelerators, focusing on low-latency and high-throughput large language model inference. The company is seeking a seasoned professional to lead the physical implementation of its AI accelerators, ensuring top-tier performance, power, and area (PPA) metrics.

Responsibilities:

• Own the physical implementation of AI accelerators from floorplanning to tapeout.
• Drive clock tree synthesis, place and route, and routing optimization to achieve timing closure.
• Manage signal integrity, IR/EM closure, ECO implementation, and metal fill for signoff-quality results.
• Oversee tapeout signoff for all physical implementation deliverables.
• Develop methodologies for power grids, power/ground tiles, and bump planning.
• Create congestion analysis and wire estimation approaches to inform early floorplan decisions.
• Define partitioning and hierarchical implementation strategies for complex designs.
• Manage Innovus-based implementation flows end to end.
• Utilize tools such as Innovus, ICC2, Tempus, PrimeTime, Voltus, RedHawk, and Calibre for implementation tasks.
• Drive closure across timing, power, area, congestion, DRC, LVS, EM, IR, and yield metrics.
• Collaborate with backend design services to align on implementation strategies and execution.
• Lead implementation reviews and ensure quality across the team.
• Apply AI-enabled techniques for automated QoR analysis, congestion prediction, routing prediction, and floorplan optimization.

Qualifications:

• 12+ years of experience in physical design from floorplanning to tapeout.
• Proven track record with multiple advanced-node tapeouts.
• Expert-level proficiency in Innovus and ICC2 implementation flows.
• Deep expertise in physical implementation, including floorplanning, clock tree synthesis, timing, and power closure.
• Hands-on experience driving full signoff across timing, power, and related quality metrics.

Skills:

• Experience with AI accelerator design (preferred).
• Familiarity with large SRAM arrays (preferred).
• Experience with SerDes and LPDDR interfaces (preferred).
• Exposure to chiplet architectures and 2.5D advanced packaging (preferred).