ASIC Verification Engineer

E-Space is seeking a Verification Engineer to join its innovative team in Saratoga, CA. The company is focused on creating advanced low Earth orbit (LEO) space systems to enhance connectivity and IoT solutions. This role involves designing, simulating, and verifying high-performance integrated circuits for applications like 5G and satellite communications.

Responsibilities:

• Verify complex digital designs across custom IP blocks, subsystems, and full-chip SoC levels.
• Translate architecture and micro-architecture specifications into executable verification plans.
• Design, develop, and maintain scalable UVM-based verification environments.
• Develop high-quality testbenches using SystemVerilog and support VHDL and mixed-language environments.
• Drive functional and code coverage, analyze results, and close coverage gaps.
• Debug complex issues using simulation, waveform analysis, assertions, and root-cause analysis.
• Collaborate closely with architects, RTL designers, and system teams.
• Document verification plans, methodologies, and results, and provide clear status updates to leadership.

Qualifications:

• Minimum of 5-10 years of experience in ASIC verification for complex digital systems.
• Deep expertise in SystemVerilog and strong working knowledge of VHDL for design and verification in mixed-language environments.
• Hands-on experience with UVM-based verification methodologies.
• Solid understanding of digital design fundamentals.
• Experience verifying industry-standard protocols.
• Strong debugging skills using simulation tools and waveform analysis.
• Excellent communication skills and ability to work effectively in cross-functional teams.

Skills:

• Advanced assertion-based verification or formal intent (bonus).
• Exposure to gate-level simulation, formal verification, emulation, or FPGA prototyping (bonus).
• Experience scaling or owning verification infrastructure for large or multi-project SoCs (bonus).
• Experience in verifying complex SoCs integrating CPUs, DSPs, and mixed-signal blocks (bonus).