Lead ASIC Digital Design Engineer

General Dynamics Mission Systems (GDMS) is seeking a Lead ASIC Digital Design Engineer with extensive experience in RTL design and complex digital hardware development. This role requires a deep understanding of the ASIC/FPGA design lifecycle and offers the opportunity for significant ownership within a collaborative team. The ideal candidate will be a self-starter who thrives with minimal supervision and is proactive in driving solutions.

Responsibilities:

• Own RTL design focusing on correctness, including bus fabric integrity and design-for-verification.
• Drive timing closure through synthesis, place and route, and static timing analysis, addressing root causes of timing failures.
• Lead verification efforts by developing and executing test and simulation plans, verifying results, and resolving failures.
• Manage JIRA triage by reviewing and prioritizing incoming issues and maintaining an actionable backlog.
• Conduct RTL code reviews, setting technical standards and providing feedback.
• Support program planning by contributing to Integrated Master Schedule (IMS) development and Earned Value (EV) reporting.
• Contribute to proposals by providing accurate technical input on ASIC/FPGA design tasks.
• Evaluate technology including foundry technologies and EDA tooling to inform design decisions.
• Collaborate with Integrated Product Teams and working groups across divisions.

Qualifications:

• 8–12+ years of ASIC/FPGA design experience, particularly as an RTL designer.
• Experience with ASIC tape-out efforts, including timing closure and physical verification.
• Familiarity with FinFET process nodes (7nm, 5nm, or similar).
• Experience with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent).

Skills:

• Strong understanding of ASIC/FPGA engineering concepts and RTL coding practices.
• Familiarity with industry-standard EDA tools for synthesis, simulation, and verification.
• Ability to operate independently, identifying and resolving problems without daily direction.
• Proficiency in JIRA for issue tracking and backlog management.
• Proficiency in Microsoft Office for documentation and communication.