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Mid-End ASIC Engineer, Principal

Published Date: July 23, 2026
Positron AI, Remote
Job Description:

Positron AI is at the forefront of developing custom hardware systems designed to enhance AI inference capabilities, offering superior performance and efficiency compared to traditional GPU systems. We are seeking a Principal Mid-End ASIC Engineer to lead synthesis, timing convergence, and logical design quality for our AI accelerator roadmap, playing a crucial role in transforming high-quality RTL into implementation-ready netlists.

Responsibilities:

  • Define and own synthesis methodology for current and future ASIC generations.
  • Establish signoff criteria for synthesis deliverables.
  • Conduct hands-on synthesis using EDA tools like Cadence Genus and Synopsys Design Compiler.
  • Develop and maintain SDC constraints and timing budgets.
  • Drive logical timing closure and optimization across various parameters.
  • Collaborate with architecture and RTL teams to mitigate timing risks.
  • Partner with backend engineers for physical-aware optimization and implementation-friendly RTL.
  • Lead cross-functional collaboration with various teams to resolve issues rapidly.
  • Serve as the synthesis technical lead with external partners, reviewing QoR and timing reports.
  • Apply AI to enhance timing analysis and engineering automation.

Qualifications:

  • 12+ years of ASIC implementation experience with successful tapeouts.
  • Expertise in synthesis methodology and flow development.
  • Deep knowledge of timing closure for complex designs.
  • Proficiency in Cadence Genus and/or Synopsys Design Compiler.
  • Strong SDC expertise and constraint development skills.
  • Understanding of RTL design principles and coding practices.
  • Experience with advanced process nodes at 5nm and below.
  • Strong Tcl and Python scripting skills for automation.
  • Excellent debugging and root-cause analysis capabilities.

Skills:

  • Synthesis methodology development
  • Timing closure optimization
  • Hands-on experience with EDA tools
  • SDC constraint development
  • RTL design principles
  • Advanced process node experience
  • Tcl and Python scripting
  • Debugging and analysis skills

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