Principal Digital Design Engineer / Chip Lead

Micron Technology is seeking a Principal Digital Design Engineer / Chip Lead to join its Interface Pathfinding team, which focuses on innovating memory and storage solutions that enhance information utilization. This role involves leading a small, experienced team in the design and validation of high-speed interface technologies, contributing to advancements in AI, ML, and advanced computing.

Responsibilities:

• Define top-level chip architecture and manage integration of hard and soft IP blocks.
• Author, review, and maintain synthesizable RTL (SystemVerilog) for control blocks and top-level integration.
• Develop and own chip-level timing constraints and define clock domain crossing strategies.
• Drive logic synthesis and optimize for performance, power, and area (PPA) targets.
• Coordinate with design verification teams to ensure high-quality verification of control logic and system behaviors.
• Manage IP integration agreements and vendor coordination for PHY hard macros and soft IP.
• Oversee the tape-out checklist sign-off process, ensuring a clean handoff to the foundry.
• Create architecture specifications and design documentation to serve as authoritative references for the team.
• Capture design decisions and lessons learned to facilitate future chip development.

Qualifications:

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of ASIC/digital design experience with at least one prior tape-out in a leadership role.
• Expert-level proficiency in SystemVerilog RTL design and coding best practices.
• Strong experience with logic synthesis tools and static timing analysis.
• Proficiency with industry-standard RTL simulation and debug tools.
• Solid understanding of CDC analysis methodologies and tools.
• Demonstrated experience integrating hard and soft IP blocks in mixed-signal environments.
• Ability to work effectively as a technical lead on a small team.
• Strong written communication skills for producing specifications and documentation.
• Experience partnering with design verification teams to define verification plans.

Skills:

• Expertise in SystemVerilog RTL design.
• Proficiency in logic synthesis tools (Synopsys Design Compiler, Cadence Genus).
• Experience with static timing analysis tools (PrimeTime, Tempus).
• Familiarity with RTL simulation and debug tools (VCS, Xcelium, Verdi).
• Understanding of CDC analysis methodologies (SpyGlass, JasperGold CDC).
• Ability to integrate hard and soft IP blocks in PHY-adjacent environments.
• Strong leadership and decision-making skills in technical contexts.
• Proficiency in leveraging AI for productivity.