Senior Analog Mixed Signal ASIC Layout Engineer

Draper is a nonprofit research and development company based in Cambridge, MA, with over 2,000 employees dedicated to solving critical national challenges across various fields, including military defense, space exploration, and biomedical engineering. The company fosters a collaborative environment that encourages innovation through multidisciplinary teamwork.

Responsibilities:

• Design and simulate circuits at transistor-level to meet architecture and requirement specifications.
• Contribute to system-level design and optimize hardware designs for performance, power, and cost.
• Evaluate hardware feasibility of complex algorithms and requirements.
• Independently contribute to complex chip architectures and designs.
• Drive solutions to complex problems, developing requirements and adapting to changes as needed.
• Contribute to business development and proposal activities.
• Develop, document, and teach best practices to less experienced engineers.
• Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitics.
• Perform other duties as assigned.

Qualifications:

• Bachelor's degree in Engineering or related field; Master's degree preferred.
• 5-7 years of experience with a bachelor's degree, 3-5 years with a master's, or 0-2 years with a PhD in ASIC Hardware Engineering or related.

Skills:

• Proficiency in integrated circuit design and understanding of semiconductors and computer architecture.
• Ability to write detailed design specifications and manage small technical teams.
• Excellent verbal and written communication skills, mathematical skills, and organizational skills.
• Strong analytical and problem-solving skills with the ability to prioritize tasks and meet deadlines.
• Experience with low power circuit design and CMOS advanced nodes below 32nm.
• Familiarity with Cadence, Siemens, and Keysight toolsets, and proficiency in implementing analog designs into full custom layout.
• Understanding of layout effects on circuit performance and experience with physical verification tools and methodologies.