Senior Principal ASIC FPGA Engineer

We are seeking an experienced ASIC Lead Engineer with a strong background in RTL design and a proven track record in the full ASIC design lifecycle. This hands-on technical leadership role requires a self-starter who can operate independently and drive progress while collaborating with a team. The ideal candidate will have extensive experience in ASIC/FPGA design, particularly in advanced process nodes, and will be responsible for defining architecture, leading RTL development, and ensuring successful tape-out of complex silicon.

Responsibilities:

• Define the ASIC/FPGA technical approach from concept through silicon, including system partitioning and microarchitecture.
• Lead detailed RTL development focusing on correctness, including bus fabric integrity and clock domain crossings.
• Navigate synthesis, place and route, and static timing analysis to meet timing in advanced process nodes.
• Serve as the primary point of contact for verification activities, developing and owning test and simulation plans.
• Own JIRA triage for the team, prioritizing work items and ensuring backlog accuracy.
• Conduct and lead RTL code reviews, providing constructive feedback to engineers.
• Contribute to Integrated Master Schedule (IMS) development and Earned Value (EV) reporting.
• Evaluate high-level design processes including synthesis, P&R, and timing analysis.
• Assess foundry technologies and EDA tooling to inform design decisions.
• Lead ASIC/FPGA technical approach on proposals and manage technical subcontracts.
• Mentor junior and mid-level engineers and contribute to improving ASIC/FPGA design processes.
• Participate in multi-divisional or multi-company Integrated Product Teams.

Qualifications:

• Bachelor's degree in Electrical or Computer Engineering, or a related field with 10+ years of relevant experience; or a Master's degree with 8+ years of experience.
• Department of Defense Secret security clearance required at time of hire.
• U.S. citizenship is required.

Skills:

• Expert-level understanding of ASIC/FPGA engineering concepts and RTL coding practices.
• Strong familiarity with industry-standard EDA tools for synthesis, simulation, and verification.
• Demonstrated ability to operate independently and drive resolution of issues.