Published Date: June 17, 2026
Palo Alto Networks, Santa Clara, CA 95054•Hybrid work
Job Description:
Palo Alto Networks is seeking a Design Verification Engineer to join their ASIC team in Santa Clara, California. The role focuses on ensuring that ASICs in next-generation firewall products meet high standards for features, performance, and reliability. The company values collaboration and innovation, encouraging employees to work together in an office setting most of the week.
Responsibilities:
- Collaborate with software, architecture, design, and verification teams to create pre-silicon verification plans.
- Plan and execute simulation test plans using coverage-driven, constrained-random methodologies.
- Develop flows, methodologies, and infrastructure for emulation.
- Create, run, and debug emulation tests in collaboration with system architects and ASIC designers.
- Define new tools and methodologies to improve quality and velocity.
- Automate verification tasks using Python for triage, coverage closure, and metrics-driven verification.
Qualifications:
- BS in Electrical Engineering, Computer Engineering, or Computer Science required; MSEE preferred.
- Minimum 5 years of experience in ASIC design verification.
- Demonstrated success in taking multiple ASIC products from concept to mass production.
Skills:
- Expertise in SystemVerilog and UVM.
- Strong technical skills in defining test plans and developing functional coverage models.
- Experience in creating scalable test benches and self-checking infrastructure.
- Proficient in debugging failures and closing coverage.
- Familiarity with networking and cybersecurity, formal property verification, and silicon validation.
- Skilled in Python, C/C++, Perl, and UNIX shell scripting for automation.
