Sr. SOC/ASIC DFT Engineer [Silicon Engineering]

SpaceX is seeking a motivated and proactive Sr. SOC/ASIC DFT Engineer to join its Silicon Engineering team. This role focuses on developing next-generation ASICs for deployment in space and ground infrastructures, contributing to the Starlink project, which aims to provide fast and reliable internet globally. The ideal candidate will work with cross-disciplinary teams to enhance the performance and capabilities of the Starlink network.

Responsibilities:

• Implement and optimize DFT architectures, including scan insertion and logic BIST using Siemens Tessent tools.
• Integrate and verify DFT IPs within subsystems.
• Set up and run ATPG tools for generating test patterns, focusing on compression and diagnosis.
• Run and debug gate-level simulations and validate DFT patterns for post-silicon bringup.
• Develop test scripts and automate processes using programming languages like Perl, Python, Tcl, or C++.

Qualifications:

• Bachelor's degree in electrical engineering, computer engineering, or physics.
• 5+ years of experience in semiconductor DFT engineering, post-silicon validation, or production testing.

Skills:

• Master's or PhD in a related engineering field is preferred.
• Experience in post-silicon bringup and yield optimization on complex SoCs or ASICs.
• Hands-on experience with ATE platforms for high-volume manufacturing.
• Collaboration with cross-functional teams to ensure DFT features meet production requirements.
• Knowledge of industry standards for testability and low-power DFT techniques.
• Experience with In-System Test, boundary scan, and functional testing in embedded systems.
• Excellent problem-solving and communication skills.