Sr. SOC/ASIC Physical Design Engineer [Silicon Engineering]

SpaceX is seeking a motivated and proactive Senior SOC/ASIC Physical Design Engineer to join its Silicon Engineering team. This role involves developing next-generation silicon for SpaceX's Starlink project, which aims to provide fast and reliable internet globally. The engineer will work with cross-disciplinary teams to enhance the performance and capabilities of the Starlink network, contributing to the company's mission of enabling human life on Mars.

Responsibilities:

• Perform partition synthesis and physical implementation steps including synthesis, floorplanning, and timing checks.
• Develop and improve physical design methodologies and automation scripts.
• Collaborate with the ASIC design team on architectural feasibility studies and design targets.
• Resolve design, timing, and flow issues, identifying solutions and driving execution.
• Run, debug, and fix signoff closure issues in static timing analysis and physical verification.

Qualifications:

• Bachelor's degree in electrical engineering, computer engineering, or computer science.
• 5+ years of ASIC and/or physical design flow development experience.

Skills:

• Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows.
• Proficiency with industry-standard EDA tools and understanding of their algorithms.
• Knowledge of deep sub-micron FinFET and CMOS solid state physics.
• Understanding of CMOS digital design principles and standard cell libraries.
• Familiarity with DFT/Scan/MBIST/LBIST and their impact on physical design flows.
• Good scripting skills in languages such as csh/bash, Perl, Python, and TCL.