Sr. Staff Engineer, ASIC Design

Ayar Labs is seeking a Sr. Staff Engineer for ASIC Design to join their innovative team in San Jose. The company specializes in co-packaged optics (CPO) technology, enabling faster and more energy-efficient data transfer for AI applications. The role involves designing, bringing up, and debugging complex digital subsystems within electro-optical digital SoCs, contributing to the advancement of next-generation AI architectures.

Responsibilities:

• Develop detailed digital algorithm specifications in collaboration with analog, photonics, and firmware engineers.
• Optimize RTL in Verilog for complex electro-optical ASICs.
• Create models and testbenches for digital and mixed-signal blocks.
• Document designs for backend ASIC engineers to facilitate physical implementation and timing signoff.
• Bring up, evaluate, and debug custom silicon using Python scripting and firmware.
• Contribute to automated design methodologies and flows for ASIC digital design.
• Engage in hands-on work with high-speed interconnects and optical systems.

Qualifications:

• BS in Electrical Engineering, Computer Engineering, or related fields.
• 5+ years of experience in ASIC design.
• Proven ability to manage technical tasks and complete projects independently.
• Mastery of Verilog and SystemVerilog for RTL design and verification.
• Proficient in ASIC verification tools (XCelium, VCS, Questa).
• Proficient in low-level programming languages (C, C++).
• Proficient in Python.
• Knowledge of digital timing constraints and ASIC tool flows.
• Experience with digital designs involving multiple clock domains and clock dividers.
• Familiarity with SOC interconnect fabrics (AMBA AXI/AHB/APB).

Skills:

• Proficient in ASIC synthesis tools (Genus, Design Compiler).
• Skilled in writing timing constraints and understanding timing analysis.
• Experience integrating custom blocks in a digital-top flow (LEF, lib, etc.).
• Experience with silicon bring-up, debug, and evaluation.
• Knowledge of FPGAs and/or microcontroller platforms.
• Familiarity with the Cadence Virtuoso design environment, schematic entry, layout, and simulation.
• Experience with DFT methodologies and flows (scan insertion, BIST, ATPG).
• Knowledge of high-speed SerDes components and optics.