Substrate IC Package Layout Design Engineer

Etched is at the forefront of frontier intelligence, developing cutting-edge hardware that includes chips, racks, software, and manufacturing solutions. With significant backing from top-tier investors and a team of leading engineers, Etched is redefining the infrastructure for the rapidly growing AI industry. We are seeking a Substrate IC Package Layout Design Engineer to lead the design of complex IC substrate packages, focusing on high-power consumption and high-speed signaling.

Responsibilities:

• Lead the design and development of complex IC substrate layouts for high-power AI processors and accelerators.
• Design large (>50mm) and complex multi-layer substrate packages with high pin counts and dense routing requirements.
• Ensure robust power delivery designs capable of supporting >700W custom silicon solutions.
• Develop high-speed signal routing solutions capable of supporting >50GHz signaling while minimizing signal integrity issues.
• Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and implement solutions in substrate layout.
• Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for thermal and electrical performance.
• Work closely with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability.
• Perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate designs.
• Develop and maintain design documentation and guidelines for future substrate designs.
• Support design reviews and provide technical guidance to junior team members.

Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of experience in IC substrate layout design for high-performance processors or accelerators.
• Extensive experience with large substrate packages (>50mm) and complex high-density layouts.
• Proven experience with high-power (700W+) package designs and robust power delivery networks.
• Expertise in high-speed signaling design (>50GHz) and mitigating signal integrity challenges.
• Strong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer design.

Skills:

• Advanced proficiency in Allegro Package Designer (including constraint management, routing, and design verification).
• Deep understanding of SI/PI principles and their application to package-level design.
• Strong analytical skills and ability to work effectively in a fast-paced, cross-functional team environment.